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Assembleur SuperH

LDC

SuperH Load to Control Register

Syntaxe

LDC Rm,SR
LDC Rm,GBR
LDC Rm,VBR
LDC Rm,MOD
LDC Rm,RE
LDC Rm,RS
LDC.L @Rm+,SR
LDC.L @Rm+,GBR
LDC.L @Rm+,VBR
LDC.L @Rm+,MOD
LDC.L @Rm+,RE
LDC.L @Rm+,RS

Description

Cette instruction permet d'entreposer l'opérande source dans le registre de contrôle SR, GBR, VBR, MOD, RE ou RS.

Algorithme

MODULE LDCSR(m) * LDC Rm,SR
   SR ← R[m] ∩ 0FFF0FFFh
   PC ← PC + 2

MODULE LDCGBR(m) * LDC Rm,GBR
   GBR ← R[m]
   PC ← PC + 2

MODULE LDCVBR(m) * LDC Rm,VBR
   VBR ← R[m]
   PC ← PC + 2

MODULE LDCMOD(m) * LDC Rm,MOD
   MOD ← R[m]
   PC ← PC + 2

MODULE LDCRE(m) * LDC Rm,RE
   RE ← R[m]
   PC ← PC + 2

MODULE LDCRS(m) * LDC Rm,RS
   RSR ← R[m]
   PC ← PC + 2

MODULE LDCMSR(m) * LDC.L @Rm+,SR
   SR ← Read_Long(R[m])∩ 0FFF0FFFh
   R[m] ← R[m] + 4
   PC ← PC + 2

MODULE LDCMGBR(m) * LDC.L @Rm+,GBR
   GBR ← Read_Long(R[m])
   R[m] ← R[m] + 4
   PC ← PC + 2

MODULE LDCMVBR(m) * LDC.L @Rm+,VBR
   VBR ← Read_Long(R[m])
   R[m] ← R[m] + 4
   PC ← PC + 2

MODULE LDCMMOD(m) * LDC.L @Rm+,MOD
   MOD ← Read_Long(R[m])
   R[m] ← R[m] + 4
   PC ← PC + 2

MODULE LDCMRE(m) * LDC.L @Rm+,RE
   RE ← Read_Long(R[m])
   R[m] ← R[m] + 4
   PC ← PC + 2

MODULE LDCMRS(m) * LDC.L @Rm+,RS
   RS←Read_Long(R[m])
   R[m] ← R[m] + 4
   PC ← PC + 2

Mnémonique

Instruction Abstrait Opcode Cycle
LDC Rm,SR SR ← Rm 0100mmmm00001110 1
LDC Rm,GBR GBR ← Rm 0100mmmm00011110 1
LDC Rm,VBR VBR ← Rm 0100mmmm00101110 1
LDC Rm,MOD MOD ← Rm 0100mmmm01011110 1
LDC Rm,RE RE ← Rm 0100mmmm01111110 1
LDC Rm,RS RS ← Rm 0100mmmm01101110 1
LDC.L @Rm+,SR SR ← (Rm), Rm ← Rm + 4 0100mmmm00000111 3
LDC.L @Rm+,GBR GBR ← (Rm), Rm ← Rm + 4 0100mmmm00010111 3
LDC.L @Rm+,VBR VBR ← (Rm), Rm ← Rm + 4 0100mmmm00100111 3
LDC.L @Rm+,MOD MOD ← (Rm), Rm ← Rm + 4 0100mmmm01010111 3
LDC.L @Rm+,RE RE ← (Rm), Rm ← Rm + 4 0100mmmm01110111 3
LDC.L @Rm+,RS RS ← (Rm), Rm ← Rm + 4 0100mmmm01100111 3


Dernière mise à jour : Mardi, le 28 juillet 2015