| Assembleur SuperH | LDS |
|---|---|
| SuperH | Load to System Register |
Syntaxe
| LDS Rm,MACH |
| LDS Rm,MACL |
| LDS Rm,PR |
| LDS Rm,DSR |
| LDS Rm,A0 |
| LDS Rm,X0 |
| LDS Rm,X1 |
| LDS Rm,Y0 |
| LDS Rm,Y1 |
| LDS.L @Rm+,MACH |
| LDS.L @Rm+,MACL |
| LDS.L @Rm+,PR |
| LDS.L @Rm+,DSR |
| LDS.L @Rm+,A0 |
| LDS.L @Rm+,X0 |
| LDS.L @Rm+,X1 |
| LDS.L @Rm+,Y0 |
| LDS.L @Rm+,Y1 |
Description
Cette instruction permet d'entreposer l'opérande source dans le registre système MACH, MACL ou PR ou le registre DSP, DSR, A0, X0, X1, Y0 ou Y1.
Algorithme
|
MODULE LDSMACH(m) * LDS Rm,MACH MACH ← R[m] SI MACH ∩ 00000200h = 0 ALORS MACH ← MACH ∩ 000003FFh SINON MACH ← MACH U FFFFFC00h FIN SI PC ← PC + 2 MODULE LDSMACL(m) * LDS Rm,MACL MACL ← R[m] PC ← PC + 2 MODULE LDSPR(m) * LDS Rm,PR PR ← R[m] PC ← PC + 2 MODULE LDSDSR(m) * LDS Rm,DSR DSR ← R[m] ∩ 0000000Fh PC ← PC + 2 MODULE LDSA0(m) * LDS Rm,A0 A0 ← R[m] SI A0 ∩ 80000000h = 0 ALORS A0G ← 00h SINON A0G ← FFh FIN SI PC ← PC + 2 MODULE LDSX0(m) * LDS Rm, X0 X0 ← R[m] PC ← PC + 2 MODULE LDSX1(m) * LDS Rm, X1 X1 ← R[m] PC ← PC + 2 MODULE LDSY0(m) * LDS Rm, Y0 Y0 ← R[m] PC ← PC + 2 MODULE LDSY1(m) * LDS Rm, Y1 Y1 ← R[m] PC ← PC + 2 MODULE LDSMMACH(m) * LDS.L @Rm+,MACH MACH ← Read_Long(R[m]) SI MACH ∩ 00000200h = 0 ALORS MACH ← MACH ∩ 000003FFh SINON MACH ← MACH U FFFFFC00h FIN SI R[m] ← R[m] + 4 PC ← PC + 2 MODULE LDSMMACL(m) * LDS.L @Rm+,MACL MACL ← Read_Long(R[m]) R[m] ← R[m] + 4 PC ← PC + 2 MODULE LDSMPR(m) * LDS.L @Rm+,PR PR ← Read_Long(R[m]) R[m] ← R[m] + 4 PC ← PC + 2 MODULE LDSMDSR(m) * LDS.L @Rm+,DSR DSR ← Read_Long(R[m]) ∩ 0000000Fh R[m] ← R[m] + 4 PC ← PC + 2 MODULE LDSMA0(m) * LDS.L @Rm+,A0 A0 ← Read_Long(R[m]) SI A0 ∩ 80000000h = 0 ALORS A0G ← 00h SINON A0G ← FFh FIN SI R[m] ← R[m] + 4 PC ← PC + 2 MODULE LDSMX0(m) * LDS.L @Rm+,X0 X0 ← Read_Long(R[m]) R[m] ← R[m] + 4 PC ← PC + 2 MODULE LDSMX1(m) * LDS.L @Rm+,X1 X1 ← Read_Long(R[m]) R[m] ← R[m] + 4 PC ← PC + 2 MODULE LDSMY0(m) * LDS.L @Rm+,Y0 Y0 ← Read_Long(R[m]) R[m] ← R[m] + 4 PC ← PC + 2 MODULE LDSMY1(m) * LDS.L @Rm+,Y1 Y1 ← Read_Long(R[m]) R[m] ← R[m] + 4 PC ← PC + 2 |
Mnémonique
| Instruction | Abstrait | Opcode | Cycle |
|---|---|---|---|
| LDS Rm,MACH | MACH ← Rm | 0100mmmm00001010 | 1 |
| LDS Rm,MACL | MACL ← Rm | 0100mmmm00011010 | 1 |
| LDS Rm,PR | PR ← Rm | 0100mmmm00101010 | 1 |
| LDS Rm,DSR | DSR ← Rm | 0100mmmm01101010 | 1 |
| LDS Rm,A0 | A0 ← Rm | 0100mmmm01111010 | 1 |
| LDS Rm,X0 | X0 ← Rm | 0100mmmm10001010 | 1 |
| LDS Rm,X1 | X1 ← Rm | 0100mmmm10011010 | 1 |
| LDS Rm,Y0 | Y0 ← Rm | 0100mmmm10101010 | 1 |
| LDS Rm,Y1 | Y1 ← Rm | 0100mmmm10111010 | 1 |
| LDS.L @Rm+,MACH | MACH ← (Rm), Rm ← Rm + 4 | 0100mmmm00000110 | 1 |
| LDS.L @Rm+,MACL | MACL ← (Rm), Rm ← Rm + 4 | 0100mmmm00010110 | 1 |
| LDS.L @Rm+,PR | PR ← (Rm), Rm ← Rm + 4 | 0100mmmm00100110 | 1 |
| LDS.L @Rm+,DSR | DSR ← (Rm), Rm ← Rm + 4 | 0100mmmm01100110 | 1 |
| LDS.L @Rm+,A0 | A0 ← (Rm), Rm ← Rm + 4 | 0100mmmm01110110 | 1 |
| LDS.L @Rm+, X0 | X0 ← (Rm), Rm ← Rm + 4 | 0100nnnn10000110 | 1 |
| LDS.L @Rm+,X1 | X1 ← (Rm), Rm ← Rm+4 | 0100nnnn10010110 | 1 |
| LDS.L @Rm+,Y0 | Y0 ← (Rm), Rm ← Rm+4 | 0100nnnn10100110 | 1 |
| LDS.L @Rm+, Y1 | Y1 ← (Rm), Rm ← Rm+4 | 0100nnnn10110110 | 1 |
Dernière mise à jour : Mardi, le 28 juillet 2015